The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which allows information to be read from a memory cell with a high speed.
In recent years, there has been a desire for fast microcomputers having an operation speed of over 100 MHz. As microcomputers become faster in operation, the operation of ROMs and flash memories which are mounted on the same chip as the microcomputers are also required to become faster. Such ROMs and flash memories are usually mounted on a chip for the purpose of customizing the chip.
The required memory capacity is also on the increase with recent enhancements in the functions of microcomputers.
Against such a background, vigorous research and development activities are being made to realize large capacity semiconductor memory devices which are capable of fast read operations. For example, a semiconductor memory device based on a hierarchical bit line method has been proposed.
M. Hiraki et al. (ISSCC Digest of Technical Papers, pp. 116-117, 453, February 1999) discloses a semiconductor memory device based on a hierarchical bit line method.
However, in accordance with the aforementioned type of semiconductor memory device, it is necessary to perform an integration operation for sensing a difference between the voltage on the main bit line and the voltage on a complementary main bit line after completing precharging of the main bit line and a sub-bit line. Therefore, in order to read information from a memory cell, a period of time (tPRC+tInteg) is required, which is a sum of the time required for precharging the main bit line and the sub-bit line (i.e., tPRC) and the time required for sensing the voltage difference (i.e., tInteg). This has presented difficulties in the realization of a fast read operation of information from memory cells.
Thus, in view of the aforementioned problems, the present invention aims to provide a semiconductor memory device which is capable of reading information from memory cells with a high speed.
A semiconductor memory device according to the present invention comprises: a differential sense amplifier having a first input node and a second input node for sensing a difference between a voltage on the first input node and a voltage on the second input node; an information read section for supplying a voltage varying in accordance with information which is read from a memory cell, the voltage being supplied to the first input node; a reference section for supplying a reference voltage to the second input node; and a control section for controlling the differential sense amplifier, the information read section, and the reference section, wherein the information read section includes: a main bit line coupled to the first input node; a select gate; a sub-bit line which is coupled to the main bit line via the select gate; a memory cell which is coupled to the sub-bit line and which is selectively activated in accordance with a voltage on a word line; a precharge section for precharging the first input node and the main bit line to a first voltage; and a reset section for resetting the sub-bit line to a second voltage which is lower than the first voltage, wherein the control section controls the precharge section, the reset section, and the select gate so that a portion of a charge which is precharged in the first input node and the main bit line is redistributed to the sub-bit line after precharging the first input node and the main bit line to the first voltage and resetting the sub-bit line to the second voltage. As a result, the aforementioned objective is accomplished.
The information read section may further comprise: a first capacitance coupled to the main bit line; and a second capacitance coupled to the sub-bit line.
A voltage on the sub-bit line after the charge which is precharged in the first input node and the main bit line is redistributed may be equal to or less than about 1 V.
The reference section may comprise: a complementary main bit line coupled to the second input node: and a precharge section for precharging the second input node and the complementary main bit line to a third voltage, wherein the third voltage is equal to a voltage which is obtained by multiplying the first voltage by a predetermined ratio.
The reference section may output the reference voltage by using a reference cell having a current performance which is substantially half of a current performance of the memory cell.
The differential sense amplifier may sense the difference between the voltage on the first input node and the voltage on the second input node through sense integration.
The sense integration may be begun while a portion of a charge which is precharged in the first input node and the main bit line is redistributed to the sub-bit line.
Another semiconductor memory device according to the present invention comprises: a differential sense amplifier having a first input node and a second input node for sensing a difference between a voltage on the first input node and a voltage on the second input node; a main bit line coupled to the first input node; a complementary main bit line coupled to the second input node; a precharge section for precharging the main bit line and the complementary main bit line to a first voltage; a plurality of subarrays arranged in a direction along which the main bit line and the complementary main bit line extend; and a control section for controlling the differential sense amplifier, the precharge section, and the plurality of subarrays, wherein each of the plurality of subarrays includes: a select gate section for selectively coupling the main bit line to one of a plurality of sub-bit lines and selectively coupling the complementary main bit line to one of a plurality of complementary sub-bit lines; a reset section for resetting the plurality of sub-bit lines to a second voltage which is lower than the first voltage, selectively releasing the resetting of one of the plurality of sub-bit lines, resetting the plurality of complementary sub-bit lines to the second voltage, and selectively releasing the resetting of one of the plurality of complementary sub-bit lines; a memory cell array including a plurality of memory cells; and a reference cell array including a plurality of reference cells, wherein: each of the plurality of memory cells is selectively activated in accordance with a voltage on a corresponding one of a plurality of word lines, and each of the plurality of reference cells is selectively activated in accordance with a voltage on a reference word line; at least one of the plurality of memory cells and at least one of the plurality of reference cells are coupled to each of the plurality of sub-bit lines; at least one of the plurality of memory cells and at least one of the plurality of reference cells are coupled to each of the plurality of complementary sub-bit lines; and the control section controls the precharge section and the plurality of subarrays so that a portion of a charge which is precharged in the main bit line is redistributed to the sub-bit line which has been released from resetting, and that a portion of a charge which is precharged in the complementary main bit line is redistributed to the complementary sub-bit line which has been released from resetting after precharging the main bit line and the complementary main bit line to the first voltage and previously resetting the plurality of sub-bit lines and the plurality of complementary sub-bit lines to the second voltage, and selectively releasing the resetting of one of the plurality of sub-bit lines and one of the plurality of complementary sub-bit lines. As a result, the aforementioned objective is accomplished.
The control section may control the plurality of subarrays so as to maintain a reset state of at least one sub-bit line adjoining the sub-bit line to which the charge has been redistributed from the main bit line, and to maintain a reset state of at least one complementary sub-bit line adjoining the complementary sub-bit line to which the charge has been redistributed from the complementary main bit line.
Another semiconductor memory device according to the present invention comprises: a differential sense amplifier having a first input node and a second input node for sensing a difference between a voltage on the first input node and a voltage on the second input node; a main bit line coupled to the first input node; a complementary main bit line coupled to the second input node; a precharge section for precharging the main bit line and the complementary main bit line to a first voltage; a plurality of subarrays arranged in a direction along which the main bit line and the complementary main bit line extend; and a control section for controlling the differential sense amplifier, the precharge section, and the plurality of subarrays, wherein each of the plurality of subarrays includes: a select gate section for selectively coupling the main bit line to one of a plurality of sub-bit lines and selectively coupling the complementary main bit line to one of a plurality of complementary sub-bit lines; a reset section for resetting the plurality of sub-bit lines to a second voltage which is lower than the first voltage, selectively releasing the resetting of one of the plurality of sub-bit lines, resetting the plurality of complementary sub-bit lines to the second voltage, and selectively releasing the resetting of one of the plurality of complementary sub-bit lines; and a memory cell array including a plurality of memory cells, wherein: each of the plurality of memory cells is selectively activated in accordance with a voltage on a corresponding one of a plurality of word lines; at least one of the plurality of memory cells is coupled to each of the plurality of sub-bit lines; at least one of the plurality of memory cells is coupled to each of the plurality of complementary sub-bit lines; and the control section controls the precharge section and the plurality of subarrays so that a portion of a charge which is precharged in the main bit line is redistributed to the sub-bit line which has been released from resetting, and that a portion of a charge which is precharged in the complementary main bit line is redistributed to the complementary sub-bit line which has been released from resetting after precharging the main bit line and the complementary main bit line to the first voltage and previously resetting the plurality of sub-bit lines and the plurality of complementary sub-bit lines to the second voltage, and selectively releasing the resetting of one of the plurality of sub-bit lines and one of the plurality of complementary sub-bit lines. As a result, the aforementioned objective is accomplished.
The control section may control the plurality of subarrays so as to maintain a reset state of at least one sub-bit line adjoining the sub-bit line to which the charge has been redistributed from the main bit line, and to maintain a reset state of at least one complementary sub-bit line adjoining the complementary sub-bit line to which the charge has been redistributed from the complementary main bit line.